Oscillator with tunable capacitor

ABSTRACT

Circuitry for controlling the oscillation frequency of an oscillator by using a digitally tunable on-chip capacitor bank. The capacitor bank includes a plurality of on-chip capacitors, each of which is independently selectable by a control signal for providing a selectable amount of capacitance to the oscillator to control the oscillator&#39;s oscillation frequency.

TECHNICAL FIELD

[0001] This invention relates to oscillator circuits, and moreparticularly to tunable oscillator circuits.

BACKGROUND

[0002] Oscillator circuits can be used to provide timing signals. Forexample, a personal computer motherboard typically has a Real Time Clock(RTC) circuit that provides an accurate 32.768 KHz oscillating signalthat is further processed to obtain the second, minute, and hour valuesused by the computer system to keep time.

[0003] The RTC circuit is typically part of an I/O controller hub chip(sometimes referred to as the south-bridge chipset), and is connected toan external crystal resonator that resonates within a narrow range ofoperating frequencies. Depending on the crystal oscillator topology, oneor more discrete external load capacitors may be connected to the RTCcircuit to tune the oscillating frequency. The values of the loadcapacitors are selected according to an initial circuit layout design sothat the RTC circuit in conjunction with the external components willoscillate at a predetermined frequency.

[0004] However, variation between different motherboard designs mayresult in placement of the load capacitors at slightly differentlocations on the motherboard, resulting in the addition of a certainamount of parasitic capacitance associated with the wiring connections.Other factors, such as tolerances in circuit components and minuterouting differences, will also affect the oscillating frequency. Becausea small variance in the oscillating frequency may significantly affectthe accuracy of the system time signal over time, individual tuning ofthe capacitance value tailored to a specific motherboard design isrequired to obtain accurate system timing signals.

[0005] The details of one or more embodiments of the invention are setforth in the accompanying drawings and the description below. Otherfeatures, objects, and advantages of the invention will be apparent fromthe description and drawings, and from the claims.

DESCRIPTION OF DRAWINGS

[0006]FIG. 1 is a schematic diagram of a computer chipset with externalcomponents that form a digitally tunable oscillator.

[0007]FIG. 2 is a schematic diagram of an on-chip capacitor bank of theoscillator circuit of FIG. 1.

[0008]FIG. 3 is a schematic diagram of a buffer circuit connected to atransmission gate switch.

[0009]FIG. 4 is a schematic diagram of an alternative embodiment of anon-chip capacitor bank.

[0010]FIG. 5 is a block diagram of an electronic device.

[0011] Like reference symbols in the various drawings indicate likeelements.

DETAILED DESCRIPTION

[0012] As will be described in more detail below, the invention isdirected towards circuitry for controlling oscillating frequency of anoscillator. In addition to the external load capacitors, the circuitryincludes on-chip capacitors, each of which is independently selectableby a control signal, and each of which provides a controllable amount ofcapacitance to the oscillator to control the oscillating frequency ofthe oscillator. The term “on-chip capacitor” means that the capacitor ismanufactured on a semiconductor chip.

[0013] Referring to FIG. 1, a tunable clock oscillator circuit 100(enclosed in dotted lines) includes two digitally selectable on-chipcapacitor banks 106 and 108 connected to a terminal X₁ and a terminalX₂, respectively, of a crystal resonator 102. Terminals X₁ and X₂ areconnected to an input terminal 110 and an output terminal 112,respectively, of an inverting amplifier 104. A feedback resistor R_(f)is connected in parallel to resonator 102 to bias amplifier 104 into alinear mode. Capacitor banks 106 and 108 are used to fine-tune theoscillating frequency of oscillator circuit 100. By selecting differentcombinations of capacitors in the on-chip capacitor banks, a differentamount of capacitance can be connected to resonator 102, therebycontrolling the oscillating frequency of oscillator circuit 100.

[0014] Two external load capacitors C_(L1) and C_(L2) are connected toterminals X₁ and X₂, respectively. The capacitance values of loadcapacitors C_(L1) and C_(L2) are selected according to specificationsgiven by the manufacturer of resonator 102. The impedance of loadcapacitors, combined with the crystal's calibrated impedance, tunes thecircuit to operate in a particular frequency in the “parallel or seriesresonance” area (depending on oscillator topology). For example,resonator 102 resonates at approximately 32.77 KHz, capacitors C_(L1)and C_(L2) have capacitances of about 15 pF, and resistor R_(f) has avalue of about 10 MegOhms.

[0015] Capacitor banks 106 and 108 each include an array of capacitorsthat are individually selectable by a set of externally provided controlsignals to provide a variable amount of capacitance. For example,capacitor banks 106 and 108 each provide a selectable amount ofcapacitance in the range of 0 to 4 pF.

[0016] Amplifier 104 and capacitor banks 106, 108 are located within anRTC circuit 122 (enclosed in dotted lines), which is part of a chipset114 of a computer system. RTC circuit 122 has a set of latches 120 thatlatches a set of control signals S₀ to S₉ that is generated byprogrammable registers 118 of chipset 114. Control signals S₀ to S₉ areused to select the individual capacitors in capacitor banks 106 and 108.

[0017] RTC circuit 122 is powered by a system power supply, as well as aseparate battery supply when the computer system is turned off. When thebattery supply is first connected to RTC circuit 122, default values areloaded into the latches to select a default set of capacitors. When thecomputer is initially booted up after RTC circuit 122 is connected tothe battery supply, a predefined register setting is read from a BIOSmemory 116 and passed through chipset registers 118 to latches 120. Thelatches store the register setting for the life of the battery, or untilthe setting is changed by chipset registers 118.

[0018] The load capacitors C_(L1) and C_(L2) are shown as beingconnected outside of chipset 114. However, it is understood that theload capacitors C_(L1) and C_(L2) may also be integrated within chipset114. It is also possible to integrate the resonator, load capacitors,resistor, and the RTC circuitry within the same package.

[0019] Referring to FIG. 2, capacitor bank 106 has a capacitor array 202that includes five capacitors, C₀ to C₄. Each capacitor is selectable byone of the control signals S₀ to S₄ through control gate switches G₀ toG₄. The capacitance values of the capacitors have a binary-weightedrelationship, such that C₄ has twice the amount of capacitance as C₃, C₃has twice the amount of capacitance of C₂, and so forth. For example,C₄=2 pF, C₃=1 pF, C₂=0.5 pF, C₁=0.25 pF, C₀=0.125 pF.

[0020] Chipset registers 118 provide control signals S₀ to S₄, which arelatched by latches 120. A control signal selects a capacitor by turningon the corresponding control gate switch so that one terminal of thecapacitor is connected to terminal 110 of crystal resonator 102. Toobtain a certain value of capacitance, chipset registers 118 select anumber of capacitors so that the sum of the capacitances of the selectedcapacitors most closely approximate the desired capacitance value.Capacitor bank 108 operates similarly to capacitor bank 106.

[0021] Capacitors C₀ to C₄ are enhancement mode P-type MOSFETs (PMOS)with the drain nodes connected to the source nodes. The gate of theMOSFET functions as one terminal of the capacitor, and the drain/sourcenode functions as the other terminal. A VCC_FILTER signal is derivedfrom the power supply signal VCC to bias the PMOS capacitors intosaturation. Most of the high frequency noise contained in the V_(cc)signal is filtered by a low pass filter composed of resistor R_(bias)and capacitor C_(bias). The VCC_FILTER signal also provides a filteredpower supply signal to a buffer circuit that drives transmission gateswitches (Figure 3). Use of the low pass filter also enables low poweroperation because capacitor C_(bias) blocks direct current from flowing.

[0022] Referring to FIG. 3, a control gate switch G₀ includes a buffercircuit 302 and a transmission gate T₀. Buffer circuit 302 is used todecouple transmission gate switch T₀ from logic circuit that producessignal S₀. This is to prevent noise generated in the chipset logiccircuit from reaching oscillator circuit 100 through transmission gateswitch T₀. Buffer circuit 302 is powered by the V_(cc) _(—) _(FILTER)signal. Use of V_(cc) _(—) _(FILTER) signal is required to preventunwanted noise in the RTC power supply signal from interfering with theoperation of oscillator circuit 100. Additional buffer circuits (havingthe same configuration as buffer circuit 302) are provided to decoupletransmission gate switches T₁ to T₉ from the logic circuits that producesignals S₁ to S₉.

[0023]FIG. 4 shows an example of an on-chip capacitor bank constructedfrom “depletion mode” NMOS transistors. An on-chip capacitor bank 402includes an on-chip capacitor array 404 and control gates G₁₀ to G₁₄.Capacitor array 404 includes depletion mode NMOS capacitors C₁₀ to C₁₄,each of which is made of an N-type MOSFET, with one terminal of thecapacitor being the gate node of the MOSFET, and the other terminal ofthe capacitor being the source-drain connected node of the MOSFET.

[0024] When NMOS capacitors are used, it is not necessary to use V_(cc)_(—) _(FILTER) signal to bias the capacitors into saturation. This isbecause a depletion mode transistor has a negative threshold voltage, soa channel is formed for all non-negative oscillation voltage levels, andthus provides a greater capacitance. Because V_(cc) _(—) _(FILTER) isused only to power the logic gates of buffer circuit 302, smaller valuesfor resistor R_(bias) and capacitor C_(bias) can be used. This allowsfor reduction of the size of the capacitor bank 402 because the “serieseffect” of the capacitor bank and the capacitor C_(bias) is eliminated.

[0025] An advantage of using tunable capacitor banks 106, 108 is thatthe computer system can dynamically adjust the oscillating frequency ofoscillator circuit 100 based on a reference time signal. The computermay log on to the Internet at regular time intervals, and compare thesystem time signal with a reference time signal, such as that providedby the NIST Internet Time Service. Based on the difference between thesystem time and reference time, chipset 114 may change the setting ofregisters 118 to select a different arrangement of capacitors incapacitor banks 106 and 108. By selecting a slightly higher or loweramount of capacitance to be connected to crystal resonator 102, chipset114 can fine-tune the oscillating frequency of oscillator circuit 100.After each adjustment, the chipset register setting are latched bylatches 120 so that oscillator circuit 100 can provide accurate timesignals even after system is powered down or off.

[0026] Another advantage of using tunable capacitor banks in anoscillator circuit is that adjustment of the oscillation frequency canbe performed after the hardware connections of the electronic componentsand circuit boards are fixed. Due to tolerances in the components andboards, the actual capacitance connected to the crystal resonator isoften slightly different from the capacitance values in the originaldesign. By adjusting the amount of capacitance provided by the tunablecapacitor banks, oscillation frequency can be tuned without altering anyhardware component or connection. The adjustment can be done manually orautomatically through appropriate software.

[0027] Use of tunable capacitor banks is not limited to the RTC circuitof computer systems. All circuits that require fine-tuning of anaccurate amount of capacitance may use a tunable capacitor bank. Allelectronic devices that require an accurate oscillating signal may usetunable capacitor banks to fine-tune the oscillation frequency. Thefine-tuning of the oscillation frequency may be used to compensatechanges in temperature and humidity, or to compensate manufacturingtolerances. Such fine-tuning of the oscillation frequency after hardwareconnections are fixed allows more flexibility in the selection ofelectronic components and circuit board layout designs.

[0028] Referring to FIG. 5, an electronic device 500 includes a chipset508 that has a RTC circuit 514 that provides a stable clock signal. RTCcircuit 514 includes two tunable on-chip capacitor banks connected toeach of the two terminals of a resonator 102. The RTC circuit 514 ispowered by both a main power supply and a battery supply so that it cankeep the oscillation even when the main power supply is shut off.

[0029] Chipset 508 includes a set of latches that store a set ofregister bit values used to control the selection of on-chip capacitorsin the capacitor banks. When chipset 508 is delivered to a manufacturerof device 500, the latches store default values. When the manufacturerdesigns a circuit board using the chipset 508, the manufacturer maydecide to modify the values stored in the latches by writing newregister bit values into a BIOS 116.

[0030] When the battery is first inserted to provide power to RTCcircuit 514, the register bit values are read from BIOS 116 and passedto the latches. Chipset 508 includes a register that stores a“capacitor-set flag” which is used to track whether the register bitvalues need to be updated. Initially, the capacitor-set flag is set to“0”. Every time electronic device 500 boots, the capacitor-set flag ischecked. If the flag is set to “1”, the latch values are not changed. Ifthe flag equals “0”, the register bit values stored in BIOS 116 are readand used to overwrite the values previously stored in the latches. Thecapacitor-set flag is then set to “1”.

[0031] A user can overwrite the register bit values stored in BIOS 116.The user then sets the capacitor-set flag to “1” to prevent BIOS 116from overwriting the user-defined settings when device 500 boots thenext time. The latch settings may also be modified by an operatingsystem (OS) running on device 500. For example, the OS may perform anadjustment to the clock signal. An accurate reference time signal isreceived from an input/output device 510. The OS controls chipset 508 toadjust the latch settings according to the reference time signal so thatRTC circuit 514 provides an accurate time signal. The OS then sets thecapacitor-set flag to “1” to prevent BIOS 116 from overwriting the latchsettings. The register bit values defined by the user or operatingsystem are maintained in the latches as long as the battery continues toprovide power to the latches and the RTC circuit.

[0032] Device 500 further includes a processor 502 that processes dataand a memory device 504 that stores data. The electronic device 500 maybe a computer, a handheld device, a consumer electronics device, or anyother device that requires an accurate time signal.

[0033] A number of embodiments of the invention have been described.Nevertheless, it will be understood that various modifications may bemade without departing from the spirit and scope of the invention. Forexample, the capacitor bank may incorporate a greater number ofcapacitors to provide a greater range of capacitance selection. Thecapacitance values of the capacitors in the capacitor bank may have somerelationship other than a binary-weighted relationship so as to providedifferent capacitance combinations. The capacitors in the capacitor bankmay be on-chip poly-capacitors or on-chip metal capacitors. Thecapacitors in the capacitor bank may even include discrete capacitorsthat are not made on a semiconductor chip. The external capacitorsC_(L1) and C_(L2) may be connected in series to resonator 102 such thatresonator 102 operate in a series resonance mode. For the capacitor bankof FIG. 2, a series connection with resistor R_(bias) and capacitorC_(bias) is not required if the oscillator signals remain above thethreshold voltage of the capacitors in the capacitor bank. Device 500may save the latch settings in a file in a hard drive 512. The file isloaded each time after device 500 is booted and used to set the chipsetregisters to select appropriate capacitors in the capacitor banks. Thisprevents the loss of latch settings in the event that the battery poweris lost. Accordingly, other embodiments are within the scope of thefollowing claims.

What is claimed is:
 1. Circuitry for controlling the oscillatingfrequency of an oscillator, the circuitry comprising: a plurality ofcapacitors, each of which is independently selectable by a controlsignal, and each of which provides a controllable amount of capacitanceto the oscillator to control the oscillating frequency of theoscillator.
 2. The circuitry of claim 1, wherein each of the pluralityof capacitors has a different capacitance than the other capacitors, anda predefined amount of capacitance is provided by a predeterminedcombination of capacitors.
 3. The circuitry of claim 2, wherein thecapacitors are drain-source connected MOSFETs.
 4. The circuitry of claim3, wherein the MOSFETs are P-type enhancement mode MOSFETs.
 5. Thecircuitry of claim 3, wherein the MOSFETs are N-type depletion modeMOSFETs.
 6. The circuitry of claim 1 wherein the capacitors are selectedfrom the group consisting of on-chip metal capacitors, on-chip polycapacitors, and discrete capacitors.
 7. The circuitry of claim 1,wherein each of the capacitors corresponds to a transmission gateswitch.
 8. The circuitry of claim 7, further comprising a set of memoryregisters to provide the control signals for selecting the individualcapacitors
 9. The circuitry of claim 8, wherein the transmission gateswitches are decoupled from the set of memory registers by a set ofbuffer circuitry.
 10. The circuitry of claim 9, wherein the set ofbuffer circuitry is powered by a filtered power signal.
 11. Thecircuitry of claim 1, wherein the oscillator includes a resonator and aninverting amplifier.
 12. The circuitry of claim 11, wherein a firstsubset of the plurality of capacitors is selectively electricallycoupled to a first terminal of the resonator, and a second subset of theplurality of capacitors is selectively electrically coupled to a secondterminal of the resonator 13 An electronic device comprising: a realtime clock for generating a system time signal, the real time clockhaving a digitally tunable oscillator for digitally adjusting anoperating frequency of the real time clock to speed up or slow down thesystem time signal; and a memory device for storing data representing aconfiguration of the digitally adjusted tunable oscillator.
 14. Theelectronic device of claim 13, further comprising a communication portfor receiving a reference time signal, wherein the digitally tunableoscillator is digitally adjusted according to the reference time signalto minimize the difference between the system time signal and thereference time signal.
 15. The electronic device of claim 13, whereinthe digitally tunable oscillator includes a capacitor bank having a setof capacitors with capacitance values in a binary-weighted relationship,the capacitors selectable through a set of control signals.
 16. A methodcomprising: generating a set of control signals to select a subset ofcapacitors from a set of capacitors; connecting the selected subset ofcapacitors to an oscillator; generating an oscillating signal using theoscillator and the selected subset of capacitors in combination; andgenerating a system time signal using the oscillating signal.
 17. Themethod of claim 16, further comprising receiving a reference timesignal, comparing the reference time signal with the system time signal,and modifying the set of control signals in response to the differencebetween the reference time signal and the system time signal to select adifferent subset of capacitors.
 18. The method of claim 17, furthercomprising saving data representing the setting of the control signalsin a memory.
 19. A method of generating a time signal comprising:generating a system time signal using a real time clock circuit that hasa tunable oscillator for adjusting an operation frequency of the realtime clock circuit; receiving a reference time signal over a network;adjusting the tunable oscillator to increase or decrease the operatingfrequency of the real time clock circuit in response to a differencebetween the system time signal and the reference time signal.
 20. Themethod of claim 19 wherein adjusting the tunable oscillator comprisesadjusting a set of control signals to modify a selection of a set ofcapacitors within a capacitor bank, the selection of the set ofcapacitors correlating to the operating frequency of the real time clockcircuit.
 21. Apparatus for providing a variable level of capacitance,comprising: a plurality of capacitors, each capacitor selectable throughan independent control signal generated by a logic circuit, the selectedcapacitors providing an amount of capacitance that is the sum of theindividual capacitances of the selected capacitors; and buffer circuitryfor decoupling the plurality of capacitors from the logic circuit toprevent noise in the logic circuit from affecting the plurality ofcapacitors.
 22. The apparatus of claim 21, further comprising a filtercircuit connected to a power supply to generate a filtered power supplysignal that is used to power the buffer circuitry.
 23. The circuit ofclaim 21, further comprising transmission gates, each of whichcorresponds to one of the plurality of capacitors and can be turned onby the independent control signal when the corresponding capacitor isselected.
 24. Apparatus comprising: a control unit configured togenerate a set of control signals, each of which independently selects acapacitor from a plurality of capacitors, the selected capacitors beingcoupled to an oscillator, the selected capacitors in combination provinga controllable amount of capacitance to the oscillator to control theoscillating frequency of the oscillator.
 25. The apparatus of claim 24in which the control unit is disposed within a computer chipset.
 26. Theapparatus of claim 24, further comprising circuitry for generating asystem time signal based on the oscillating frequency of the oscillator.27. The apparatus of claim 26, further comprising a memory for storingthe configuration of the set of control signals, and a data processingunit that processes data based on the system time signal.